BibTeX:

@article{IJIRSTV1I8009,
     title={High speed Low Power Viterbi Decoder for TCM Decoders using Xilinx},
     author={T. Mahesh kumar and P.Vijai Bhaskar},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={1},
     number={8},
     pages={30--38},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV1I8009.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.

Viterbi Decoder, VLSI, Trellis Coded Modulation (TCM).