BibTeX:

@article{IJIRSTV1I11195,
     title={Design and Implementation of Pipelined Floating Point Fast Fourier Transform Processor},
     author={Veera Kamat Dhakankar and Prof. Sonia Kuwelkar},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={1},
     number={11},
     pages={512--516},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV1I11195.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

There are several methodologies and techniques that already offer hardware and software solutions for computing Fast Fourier Transform (FFT), which have advantages for specific applications. These solutions are developed for running in several platforms, such as GPU, DSP, FPGA and ASIC and they are usually described in C/C++ language or HDL. Implementation intended for reconfigurable logic is usually described in HDL, such as VHDL or Verilog. Different FFT algorithms have been proposed to exploit certain signal properties to improve the trade-off between computation time and hardware requirements. For years the common practice for implementing FFTs has been to run them on a digital signal processor (DSP). But as FPGAs have evolved and have begun to accommodate function specific computing cores, FPGAs are beginning to displace DSP as the optimum FFT solution. In this project the implementation of FFT radix 2 algorithm design of floating point FFT in FPGA is discussed. The VHDL Design was tested using Modelsim measure its performance in term of speed and scalability and also the processor is synthesized on an FPGA to measure the performance parameters such as maximum operating frequency, area and power consumption. Synthesis tool is Xilinx ISE Design Suit 10.1 and FPGA is Sparten III.

FFT processor, Pipelined processor