Design of D-Flip Flop Using MTCMOS Technique |
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BibTeX: |
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@article{IJIRSTV1I12048, |
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Abstract: |
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CMOS provide low power dissipation, comparatively high speed , high noise margin. D-flip flop is designed using mtcmos technique in which one transistor being clocked by short pulse train which is true single phase clocking (tspc) flip flop . In this paper D-flip flop implemented with mtcmos method is built using tanner eda software and the output is verified. In tanner, schematic diagram is designed in s-edit, truth table is observed on t-edit, the required waveforms are shown in w-edit, layout is specified in L-edit. |
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Keywords: |
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TSPC, tanner eda, CMOS, S-edit, T-edit, W-edit, L-edit |
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