BibTeX:

@article{IJIRSTV2I1036,
     title={Layout Design of CMOS Buffer to Reduce Area and Power},
     author={Mohd Shariq Mahboob and Rajesh Mehra},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={2},
     number={1},
     pages={22--25},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV2I1036.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

High speed digital Input buffer circuits are used in a wide variety of digital applications. A very common application of these input buffers is in memory devices. Memory circuits needs clean and full level digital data in the memory array. The digital data traveling through various digital circuitries gets distorted by adding delays in the signals like low voltage signal levels, slow fall and rise times, etc. The buffer circuits take these input signals with imperfections and convert them in to full digital logic levels by ‘slicing’ the data signals at correct levels which depends upon the switching point voltage. In this paper layout of CMOS buffer is drawn; first one is auto-generated and second one is semi-custom layout. Then a comparison of various properties of the two layouts is done.

Buffer, CMOS technology, Leakage Power, Threshold Voltage, VLSI