BibTeX:

@article{IJIRSTV2I8044,
     title={Design of Arithmetic Logic Unit Using Complementary Metal Oxide Semiconductor Galois Field},
     author={Prof. T. R. Harinkhede, Ms. Pooja R. Thakare, Ms. Divya R. Savale, Ms. Koyal T. Karare and Ms. Manisha P. Dongre},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={2},
     number={8},
     pages={91--95},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV2I8044.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

Interconnection increases the delay, area and energy consumption in complementary metal oxide semiconductor (CMOS) digital circuit. For design circuitry in VLSI, multiple-valued logic (MVL) plays a very vital role. Multiple-valued logic is an apparent extension of binary logic where any proposition can have more than two values. Average power requirement can be decreased using the concept of level transition in multiple-valued logic. MVL is also helps to reduce the number of interconnections. It provides the key benefit of higher density per integrated circuit area compared to traditional binary logic. In this paper, we present an application of these circuits with response to Galois field operations and also present a quaternary converter circuits using Down Literal Circuit (DLC). Arithmetic operations such as addition and multiplication are the two basic operations in Galois field. Tanner has created a software platform that is cost-effective and easy to use.

Down Literal Circuit, Galois field, Multiple-valued logic, Quaternary logic, Standard CMOS technology, VLSI