BibTeX:

@article{IJIRSTV3I7034,
     title={An Analysis and Design of High Performance Power Consumption Double Tail Comparator using Gated Clock and Power Gating Techniques},
     author={Dr. V. Sujatha},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={3},
     number={7},
     pages={191--197},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV3I7034.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

In the modern digital world, Analog to Digital Conversion is the major role in every hardware device. Power consumption is most important parameters for concern in CMOS technology. The main requirements of the ADC are very low power consumption, low noise, less hysteresis, less offsets and high speed. Comparators are the basic elements for designing the modern analog and mixed signal systems. The speed and area is the main factors for very high speed applications. For past several years, the technology scaling is the most important procedures for the improvement performance of circuits are in terms of the power, speed etc. In this article, analysis and design of double tail comparator transistor is done in terms of power, delay and glitches. Comparator is the important circuit in the digital design and is defined in terms of power and speed, which are the most important factors of attaining the complete performance of ADCs. Several ADCs required small delay, Low power comparator with small die size. The accuracy of comparators is mainly defined with to its power consumptions and speed. The comparators are mainly achieving the overall high performance of ADC. The high speed comparators suffered from low voltage supply. Threshold voltage of the devices is not scaled at the same time, as the supply voltage of the device. In modern CMOS a technology of the double tail comparator is designed by the using dynamic method, it mainly reduces the power and voltage. The designed modified double tail comparator is simulated with using Tanner EDA tool and analysed that, it consumes the power of about 35µw with the delay of 1.14ns.

Double Tail Comparator, ADC, Dynamic Comparator, Glitches