BibTeX:

@article{IJIRSTV4I9031,
     title={FPGA Realization of Optimized Digital Down Converters for WCDMA and CDMA 2000},
     author={Prasanna S. C. and Joy Vasantha Rani S. P.},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={4},
     number={9},
     pages={115--124},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV4I9031.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

This paper aims to provide an efficient design of digital down converters (DDC) that are used in receiver section of software defined radios (SDR). SDR is a radio in which some or all of the physical layer functions are software defined, making it flexible, upgradable and reliable wireless communication structure. In digital signal processing (DSP), a digital down-converter, converts a digitized real signal centered at an intermediate frequency (IF) to a baseband complex signal centered at zero frequency. In addition to down conversion, DDC’s typically decimate to a lower sampling rate. WCDMA and CDMA 2000 are some of the third generation applications of SDR and thus the implementation of optimized DDC structure for these applications is presented. The DDC is first designed in MATLAB Simulink tool (R2012B) and codes are generated using MATLAB. Then the verilog codes are written for the same structure using proposed SHIFT and MUX based multiplier. Both the designs are synthesized on Altera Cyclone II EP2C35F672C6 field programmable gate array (FPGA). The model built using proposed SHIFT and MUX based multiplier provides an area improvement of 77.01% and 78%, speed improvement of 26.73% and 27.05% for WCDMA DDC and for CDMA 2000 DDC respectively, making it suitable for SDR application.

DDC, FPGA, SDR, SHIFT and MUX