BibTeX:

@article{IJIRSTV1I11090,
     title={Design High Speed Conventional D Flip-Flop using 32NM CMOS Technology},
     author={Mr. PRATHAMESH G. DHOBLE and Mrs. AVINASH D. KALE},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={1},
     number={11},
     pages={178--184},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV1I11090.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The propose circuit will be faster than conventional circuit as it will be a fast reset operation. The circuit will be consuming less power as it prevents short circuit power consumption. The circuit operates at low voltage power supply.

Phase Locked Loop (PLL), D-ff, Phase Frequency Detector (PFD) and Voltage Control Oscillator (VCO)