BibTeX:

@article{IJIRSTV1I12036,
     title={Power Efficiency of Half Adder Design Using MTCMOS Technique in 35 Nanometre Regime},
     author={Priyanka Singh Yadav and Varun Kumar Pandey},
     journal={International Journal for Innovative Research in Science & Technology},
     volume={1},
     number={12},
     pages={111--117},
     year={},
     url={http://www.ijirst.org/articles/IJIRSTV1I12036.pdf},
     publisher={IJIRST (International Journal for Innovative Research in Science & Technology)},
}

A novel high speed low power half adder cell is proposed in this paper. The critical path consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power consumption than the standard implementation of the half adder. In this paper a MTCMOS (Multi Threshold Complementary Metal Oxide Semiconductor) technique is proposed to reduce the leakage current and leakage power also and got better result as compared to standard half adder cell. MTCMOS is an effective circuit level technique that improves the performance and design low power cell by utilizing both low and high threshold voltage transistors. Leakage current of half adder is reduced by 50.24% using MTCMOS technique as compared to CMOS technique. Leakage power consumption of the half adder therefore reduced by 32.21% as compared to CMOS technique. All the simulation result based on 35 nm CMOS technology and simulated by cadence tool.

Half Adder, High Speed, Low Power, MTCMOS, CMOS